Altera JTAG UART wrapper for Bluespec
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Updated
Mar 27, 2014 - C
Altera JTAG UART wrapper for Bluespec
Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.
fibonacci number calculator written in Verilog-HDL
Digital Systems Laboratory UIUC FA 2016
Design MMU for socfpga-linux 4.11. Test with Altera DE2-115.
A coocbook of HDL (primarily Verilog) modules
Driver - Library for C applications using Altera's UART Core through Avalon Bus on Cyclone V.
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