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Evaluation of timing performance of deep neural networks workloads accelerated on Versal AI Engine in presence of contention on shared resources, mainly caused by ARM Cortex A72 dual-core microprocessor.
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Nov 6, 2023 - Jupyter Notebook
Template for using Xilinx Vivado and SDK with CMPE-661 (HWSW Crypto) projects in a version control friendly way.
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Jun 12, 2023 - VHDL
C library for shared memory and messaging using inter processor interrupts.
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May 7, 2023 - C
Design and Analysis of an FPGA-based Wallace Multiplier.
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Jan 20, 2024 - Jupyter Notebook
Zynq-7000 and Zynq UltraScale+ PS side drivers for SdCard.
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Mar 6, 2024 - C
Team John Cena's Entry for the 2017 PYNQ Hackathon
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Oct 9, 2017 - Jupyter Notebook
Useful scripts to run and configure InTime with the Xilinx Vivado tools.
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Sep 6, 2021 - Verilog
Running your application from DDR memory & BPI flash using SREC bootloader
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Aug 12, 2021
Implementation of a sampler using the XADC mounted on the Arty A7-35T development board and the PmodAD1 by Digilent (AD7476A).
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Apr 2, 2022 - VHDL
Example workflow project for firmware development in Vitis.
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Feb 19, 2023 - C
A TFTP server running on Zynq-7000
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May 15, 2024 - C
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Feb 12, 2018
A microprocessor implemented in VHDL
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Feb 4, 2017 - C++
Keep Xilinx Vivado projects as minimal git repositories. A fork of https://github.com/Digilent/digilent-vivado-scripts
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Nov 23, 2021 - Tcl
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