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178 Open 253 Closed
178 Open 253 Closed
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Issues list

[GHDL / Modelsim] Simulation fails if path contains whitespaces bug Something isn't working
#635 opened Jul 15, 2024 by gfcwfzkm
TerosHDL Evaluate don't work well in V6.0.1 bug Something isn't working
#634 opened Jul 6, 2024 by narutozxp
verilog snippets error bug Something isn't working
#632 opened Jun 28, 2024 by narutozxp
Wrong port direction in Module documentation when `ifdef bug Something isn't working
#631 opened Jun 27, 2024 by niciki-niciki
The autocomplete suggestion does not work for unsaved files. bug Something isn't working
#630 opened Jun 27, 2024 by narutozxp
verilog testbench bug Something isn't working
#629 opened Jun 20, 2024 by deleteTh
2
Schematic generation successfulness depends on project file order if libraries are used bug Something isn't working
#628 opened Jun 19, 2024 by ila-embsys
3
SystemVerilog package import support enhancement New feature or request
#626 opened Jun 19, 2024 by gtaylormb
Feature: Format selection enhancement New feature or request
#625 opened Jun 19, 2024 by ckuhlmann
Schematic viewer dosen't work bug Something isn't working
#624 opened Jun 19, 2024 by deleteTh
7
Formatter rules enforcing bug Something isn't working
#619 opened May 30, 2024 by knyfi
5
Error schematic generation if top units more than one on VHDL files bug Something isn't working
#614 opened May 20, 2024 by ila-embsys
2
vscode extension TerosHDL doesn't work after installation in vscode bug Something isn't working
#613 opened May 15, 2024 by mrBitman
2
Go to definition doesn’t work bug Something isn't working
#611 opened May 3, 2024 by NickTxD
Vending_Machine bug Something isn't working
#608 opened Apr 19, 2024 by FinnNGrace
VHDL code completion improvement (?) enhancement New feature or request
#607 opened Apr 15, 2024 by ungultig1
1
"PORT" in the beginning of a VHDL generic name messes up the formatting with Standalone formatter bug Something isn't working
#602 opened Apr 10, 2024 by am9417
Display errors in incorrect file (full path instead of shortcut) bug Something isn't working
#601 opened Apr 10, 2024 by AviadMal
Markdown multiline code block displayed as single line bug Something isn't working documenter
#598 opened Apr 3, 2024 by SebastianHambura
6
No QuestaSim in Tools:General bug Something isn't working linter
#597 opened Apr 3, 2024 by DVCoder
Documentation for VHDL record types documenter enhancement New feature or request
#596 opened Apr 1, 2024 by james-ziegler
1
VHDL package documentation not being generated like entities bug Something isn't working documenter
#595 opened Apr 1, 2024 by james-ziegler
Feature Request: "Insert instance template of..." to insert component instances from libraries enhancement New feature or request
#592 opened Mar 23, 2024 by ckuhlmann
VSG command output to vscode- output enhancement New feature or request linter
#591 opened Mar 14, 2024 by ungultig1
Schematic viewer out put:[error] Yosys failed. bug Something isn't working schematic
#590 opened Mar 11, 2024 by internet96
8
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