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@chipsalliance

CHIPS Alliance

Common Hardware for Interfaces, Processors and Systems

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🔗 chipsalliance.org | 📫 [email protected]

The CHIPS Alliance develops high-quality, open source hardware designs and tools relevant to ASICs and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks, as well as open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.


The CHIPS Alliance hosts multiple open source Projects, which are Workgroups.

Popular repositories Loading

  1. chisel chisel Public

    Chisel: A Modern Hardware Design Language

    Scala 3.8k 578

  2. rocket-chip rocket-chip Public

    Rocket Chip Generator

    Scala 3.1k 1.1k

  3. verible verible Public

    Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

    C++ 1.3k 198

  4. riscv-dv riscv-dv Public

    Random instruction generator for RISC-V processor verification

    Python 974 319

  5. Cores-VeeR-EH1 Cores-VeeR-EH1 Public

    VeeR EH1 core

    SystemVerilog 791 216

  6. firrtl firrtl Public

    Flexible Intermediate Representation for RTL

    Scala 705 175

Repositories

Showing 10 of 99 repositories
  • Cores-VeeR-EL2 Public

    VeeR EL2 Core

    chipsalliance/Cores-VeeR-EL2’s past year of commit activity
    SystemVerilog 236 Apache-2.0 69 27 21 Updated Jul 16, 2024
  • synlig Public

    SystemVerilog support for Yosys

    chipsalliance/synlig’s past year of commit activity
    Verilog 146 Apache-2.0 18 64 11 Updated Jul 16, 2024
  • t1 Public
    chipsalliance/t1’s past year of commit activity
    Scala 95 Apache-2.0 19 14 14 Updated Jul 16, 2024
  • chipsalliance/synlig-logs’s past year of commit activity
    0 0 0 0 Updated Jul 16, 2024
  • caliptra-sw Public

    Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

    chipsalliance/caliptra-sw’s past year of commit activity
    Rust 49 Apache-2.0 35 73 45 Updated Jul 16, 2024
  • verilator Public Forked from verilator/verilator

    Verilator open-source SystemVerilog simulator and lint system

    chipsalliance/verilator’s past year of commit activity
    C++ 33 LGPL-3.0 570 0 1 Updated Jul 16, 2024
  • f4pga Public

    FOSS Flow For FPGA

    chipsalliance/f4pga’s past year of commit activity
    Python 341 Apache-2.0 45 13 12 Updated Jul 16, 2024
  • chisel Public

    Chisel: A Modern Hardware Design Language

    chipsalliance/chisel’s past year of commit activity
    Scala 3,838 Apache-2.0 578 303 (1 issue needs help) 148 Updated Jul 16, 2024
  • tac Public

    CHIPS Alliance Technical Advisory Council

    chipsalliance/tac’s past year of commit activity
    5 Apache-2.0 21 19 1 Updated Jul 15, 2024
  • firrtl-spec Public

    The specification for the FIRRTL language

    chipsalliance/firrtl-spec’s past year of commit activity
    TeX 35 26 23 18 Updated Jul 15, 2024