A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

An AI-driven solution enhances construction site safety using the YOLOv8 model for object detection. It identifies hazards like workers without helmets or safety vests, workers near machinery, and workers near vehicles. Post-processing algorithms further improve detection accuracy.

Verilog Implementation of an ARM LEGv8 CPU

Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.

An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) of UM-SJTU JI.

ARM Processor, Computer Architecture laboratory, University of Tehran

Smart Building Evacuation Ontology

Python GUI-based hazard video labelling

Design and development of a complete RISC CPU with: five stage pipeline, forwarding, automatic hazard detection, BTB using LRU policy replacement, four-cycle hardware multiplier.

Verilog Implementation of an ARM LEGv8 CPU

Computer organisation and architecture assignments

A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.

A paper exploring emotional contagion within the context of crowd simulation.

MIPS implementation

ahead of the weather curve

5-stage pipelined 32-bit MIPS processor

Optical sensor to detect hazardous gas in corrosive environment. Showcasing my Raspberry Pi project combining electrical engineering and sensor detection.

The research mainly aims to identify through classification algorithms if one day, based on its climatic features and concentrations of harmful elements in the air, it turns out to be harmful (or not) to the health of citizens in the Milan metropolis. A second prediction model was adopted to predict daily mean PM2.5 values.