HDL libraries and projects
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Updated
Jul 16, 2024 - Verilog
HDL libraries and projects
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
Digital logic design tool and simulator
Verilator open-source SystemVerilog simulator and lint system
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
GPGPU microprocessor architecture
Must-have verilog systemverilog modules
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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