verilog
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XLS: Accelerated HW Synthesis
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Jul 16, 2024 - C++
Fully parameterizable uart (data width, clock frequency, parity bit [ON/OFF];[ODD/EVEN], stop bit length, baud rate, seniority [DESC/ASC])
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Jul 16, 2024 - SystemVerilog
Hardened RISC-V core
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Jul 16, 2024 - SystemVerilog
Python Templated Verilog
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Jul 16, 2024 - Rust
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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Jul 16, 2024 - Verilog
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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Jul 16, 2024 - Verilog
Sol-1: A CPU/Computer System made from 74 series logic.
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Jul 16, 2024 - C
A framework for simulating digital hardware
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Jul 16, 2024 - Python
An agile package manager and extensible build tool for HDLs
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Jul 16, 2024 - Rust
📚This repository consists of some LeetCode problem solutions.
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Jul 16, 2024 - Python
HDL libraries and projects
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Jul 16, 2024 - Verilog
KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
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Jul 16, 2024 - C++
A flexible and scalable development platform for modern FPGA projects.
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Jul 16, 2024 - Python
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